- Author
- Shanqing Lin, Mohammad Alian and Babak Falsafi, on the ACM SIGARCH blog
- Published
- 8 June 2026
- Kind
- Opinion blog post by researchers, with a results table and figures
- Original
- www.sigarch.org/the-return-of-rigorous-full-system-timing-simulation/
- Subject
- Systems and hardware
- Themes
- Checking the work, Close to the machine
What it is
Three university researchers write for the Computer Architecture Today blog. The post asks what to measure, how long, and with which metric. It ends with a list of open problems.
What it says
- Detailed timing simulation is so slow that it can take months to simulate seconds.
- Full-system simulation matters because the OS, interrupts, I/O and devices shape real performance.
- Capturing performance variability for one core needs five to 120 seconds of target execution.
- Total IPC can mislead on multicore workloads, so U-IPC is often a better proxy.
- A single window of 100 million to one billion instructions may give wrong conclusions.
- Statistical sampling bounds the error in estimates and gives quantified confidence.
- Sampling shifts the bottleneck to the functional simulator, which runs at about 6 MIPS.
What evidence it gives
The post reports its own experiments on a simulated ARM Neoverse N1 core. A table of speeds and a figure of sampling errors are described in the text. It cites earlier sampling work such as SMARTS and SimPoint.
Interests and limits
The text was read in full, but the table and figures were not available. The authors favor the sampling approach. Lin is the principal developer of QFlex v3.0. The post presents QFlex as the state-of-the-art framework. The post is an opinion piece with a disclaimer that views are personal. Results cover server workloads on one ARM core design.